Method for making an electronic component with self-aligned drain and gate, in damascene architecture

ABSTRACT

A method for fabricating an electronic component with a self-aligned source, drain and gate. The method includes forming a dummy gate on a silicon substrate, in which the dummy gate defines a position for a channel of the component. The method also includes at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask, superficial, self-aligned siliciding of the source and drain, depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain. Further, depositing the at least one contact metal layer includes depositing a first metal layer and, above the first metal layer, a second metal layer having a greater mechanical resistance to polishing than the first metal layer. In addition, a thickness of the first metal layer is less than the height of the dummy gate, and a total thickness of the first and second layers is greater than the height of the dummy gate. Further, the first metal is chosen from among tungsten and titanium, and the second metal is chosen from among TaN, Ta and TiN.

TECHNICAL FIELD

The present invention concerns a method for fabricating electroniccomponents with self-aligned source, drain and gate. The componentsconcerned by the invention may be insulated gate transistors such as MOStransistors (Metal Oxide Semiconductor) for example, or electronicmemories with a dual gate, that is to say with a command gate and afloating gate.

The method of the invention particularly concerns the fabrication ofthese components on a solid silicon substrate or on a thin layersubstrate such as a substrate of SOI type (Silicon on Insulator).

The invention finds applications in numerous microelectronic areas,ranging from power switching to hyperfrequency circuits, not forgettingmemory circuits.

STATE OF PRIOR ART

Methods for producing transistors using self-aligning techniques areknown, for example, from documents (1) and (2) whose references aregiven at the end of this description.

Document (1) in particular, concerns the fabrication of a MIS transistor(Metal Insulator Semiconductor). It describes a method according towhich a dummy gate is used to fix the location and size of a final gatethat is subsequently formed. The final gate is preferably in a materialhaving low resistivity, such as metal for example, so as to reduce gateresistance and to increase the cut-off frequency of the transistor.

Document (2) indicates a method which suggests siliciding the source anddrain regions, so that the source and drain access resistances can alsobe reduced. The method of document (2) remains relatively complexhowever.

DISCLOSURE OF THE INVENTION

The invention sets out to propose a method for fabricating componentswhich is different to the methods described in the documents indicatedabove, and with which it is possible to further reduce gate, source anddrain resistances.

Another purpose is to put forward such a method whose application issimplified.

A further purpose is to make available such a method which allowsgreater miniaturization of the components and therefore greater circuitintegration.

Finally, another purpose, connected with the above aspects, is to putforward a method with which it is possible to obtain transistors havinga particularly high cut-off frequency.

To achieve these purposes, the subject of the invention is moreprecisely a method for fabricating an electronic component withself-aligned source, drain and gate, comprising the following steps:

a) forming a dummy gate on a silicon substrate, said dummy gate defininga location for a channel of the component,

b) implanting doping impurities in the substrate, to form a source anddrain either side of the channel, using the dummy gate as implantingmask,

c) self-aligned superficial siliciding of the source and drain,

d) depositing at least one, so-called contact, metal layer, whose totalthickness is greater than the height of the dummy gate, and polishingthe metal layer stopping at the dummy gate.

e) replacing the dummy gate by at least one final gate, separated fromthe substrate by a gate insulating layer, and electrically insulatedfrom the source and drain.

By means of the contact metal layer, but also on account of theself-aligned siliciding of the source and drain, the access resistanceof the source and drain may be particularly reduced despite the verysmall dimensions of the component.

In addition, by having recourse to a dummy gate, it is possible, at theend of the method, to obtain a final gate that is self-aligned on thesource and drain regions. This type of structure is particularly suitedto reduced component sizes, and in particular to gate lengths of lessthan 0.10 μm.

According to one particular embodiment of the method, the formation ofthe dummy gate may advantageously comprise the depositing of a firstlayer of material, a so-called stress adaptation layer, and of a secondlayer of material, a so-called polish stop layer, and the forming ofthese layers by etching using a mask defining the dimensions, the shapeand positioning of the gate.

At first view the essential role of the dummy gate is simply to “reservea site” for the final gate that is subsequently made. However, thechoice of a dual-layer dummy gate facilitates the subsequent steps ofthe method. The first layer is preferably a layer having a coefficientof thermal expansion and an average mesh parameter close to that of thematerial of the substrate. For monocrystalline silicon substrates, thestress adaptation layer may therefore, for example, be a layer ofamorphous or polycrystalline silicon. In addition, the depositingtechnique for these materials is easy to implement and well known.

The material of the second layer may, preferably, be chosen to have goodresistance to abrasion and polishing. It therefore provides for betteruse of the dummy gate as stop mark during the polishing operation of thecontact metal.

According to another aspect of the invention, the sides of the dummygate may be lined with one or more layers of side spacers. By layer ofside spacers is meant a layer of dielectric material which lines theside walls of a gate, that is to say the sides substantiallyperpendicular to the substrate carrying the gate. Advantage may be takenof the layers of side spacers when forming the source and drain, byusing them as additional implanting masks. The use of side spacers forimplantation, known in itself, makes it possible to obtain source anddrain regions having gradual impurity concentrations.

Within the scope of the invention, when placed in position beforesiliciding, the spacers also protect the dummy gate from siliciding, andprovide for a greater choice of materials for the latter.

Finally, the side spacers may advantageously be used in the remainder ofthe method as electric insulating means for the final gate from thelayer of contact metal.

The side spacers may be single layer spacers or, preferably, twin-layerspacers. Here again, a first layer of silicon oxide makes it possible tolimit contact stresses with the gate and substrate—the spacerseffectively coming into contact with a small portion of the substrate. Asecond layer of silicon nitride on the other hand is well adapted toprotecting the dummy gate both against oxidation and against siliciding.

Step d) mentioned above for depositing the contact metal may, accordingto one improvement, include the depositing of a first layer of metalthen, on top of the first layer, the depositing of a second metal layerhaving mechanical resistance to polishing that is greater than that ofthe first layer. The thickness of the first metal layer is thereforechosen to be smaller than the height of the dummy gate. However, thetotal thickness of the first and second layers is greater than theheight of the dummy gate.

The purpose of the second metal layer is to reduce the so-called“dishing” phenomenon of polishing. This phenomenon leads to fastererosion of the polished material in the higher step regions than in thelow regions. In other words, the depositing of two contact metal layersunder the above-described conditions makes it possible, after polishing,to obtain a free surface having excellent planarity.

The contact metal, or at least the first layer of this metal, extendsthe source and drain providing for very low access resistance to theseregions.

When polishing reaches the top of the dummy gate, or starts to enter it,it produces separation in the gate region of the metal in contact withthe source from the metal in contact with the drain. Further etching(which does not directly form part of the method of the invention) makesit possible to cut the contact metal outside the active region crossedby the gate, and hence to complete the electric insulation between drainand source.

The layers of contact metal are formed before the replacement of thedummy gate by the final gate. Therefore, in order to prevent thematerial of the final gate, preferably having low resistivity, fromshort-circuiting the source and drain, it is necessary to provide forsurface insulation or the contact layers in the source and drainregions. This operation could optionally be conducted by depositing alayer of dielectric material. According to one particular aspect of theinvention however, the method may comprise superficial oxidation of themetal layers. Oxidation can provide a simple, sure guarantee of electricinsulation between source, gate and drain. In addition it avoids anymasking operation.

In the subsequent steps of the fabrication of the component, it ispossible to make openings in the oxide of the contact metal layers toinsert contact points for interconnection lines.

The removal of the dummy gate may comprise one or more selective etchingoperations to remove its component layers. This is followed by theplacing in position of a gate insulation layer on the substrate, in thewell left by the dummy gate.

A following step consists of placing in position one or more layers ofconductor material, or at least having low resistivity, optionallyseparated by a dielectric layer. These layers form one or more gates.

More precisely, when the component it is desired to produce is atransistor, one or more conductor layers are provided to form a singlegate.

On the other hand, if the desired component is a memory, it is possiblefirstly to deposit a first conductor layer and then a second conductorlayer, separated from the first conductor layer by a layer of dielectricmaterial. The first and second conductor layers then respectively formthe floating and command gates. The dielectric layer forms an inter-gateinsulating layer.

It is to be specified that the conductor and dielectric layers mentionedabove may be homogeneous or they may be formed of stacks of severalsub-layers.

The layer or layers which form the gate structure are preferablydeposited with an overall thickness that is the same as or more than theheight of the removed dummy gate, so as to be able to undergo polishing.

Other characteristics and advantages of the invention will becomeapparent on reading the following description, with reference to thefigures of the appended drawings. This description is solely given forillustrative purposes and is non-restrictive.

SHORT DESCRIPTION OF THE FIGURES

FIGS. 1 to 3 are illustrations, in the form of diagrammaticcross-sections, showing the fabrication steps for a component with adummy gate.

FIGS. 4 to 5 are cross-section diagrams illustrating the formation ofsource and drain accesses for a component according to FIG. 3.

FIG. 6 is a cross-section diagram of a component according to FIG. 5 andillustrates an electric insulating step of the source and drainaccesses.

FIGS. 7 to 9 are cross-section diagrams illustrating the replacement ofthe dummy gate by a final gate.

FIGS. 10 and 11 are cross-section diagrams illustrating a variant of thesteps in FIGS. 8 and 9 for fabricating another type of component.

FIG. 12 is a cross-section view of a portion of an integrated circuitwith components according to the invention, and illustrates thefabrication of an interconnection.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Identical, similar or equivalent parts in the figures described belowcarry the same numerical references so as to facilitatecross-referencing from one figure to another. Also, even though thefollowing description only concerns the fabrication of components on asolid substrate, in silicon in this case, it is to be emphasized thatthe methods remain the same for forming components on insulated thinlayer substrates, such as substrates of SOI type (Silicon On Insulator).

FIG. 1 shows a silicon substrate 100 whose surface has been oxidized inorder to form a silicon oxide layer 102, a so-called pedestal layer.

On layer 102 are successively deposited a layer of polycrystalline oramorphous silicon 104, then a layer of silicon nitride 106. These layerstogether form a stack 110. The total thickness of layers 104 and 106 isin the order of 100 to 300 nm for example, and substantially correspondsto the thickness of the transistor gate which is finally obtained at theend of the method of fabrication.

An etching mask 108, shown in a dashed line, such as a mask ofphotosensitive resin, is formed on layer 106 of silicon nitride. Thismask defines the positioning, the size and the shape of a dummy gatewhich it is desired to fabricate in stack 110.

Layers 102, 104 and 106 of stack 110 are removed by etching, with theexception of a portion protected by the mask 108.

This portion of the stack forms the body of the dummy gate, referenced112 in FIG. 2.

The formation of the dummy gate is followed by a first ion implantationat low dose. Depending upon whether the component it is desired toproduce is of PMOS or NMOS type, the ions are chosen so as to make zonesof p or n type conductivity. They may for example be boron ions for PMOScomponents and phosphorus or arsenic ions for NMOS components.

The first implantation is followed by the formation of side spacers 114,116 on the side or sides of the dummy gate, visible in FIG. 2.

The side spacers comprise a first layer of silicon oxide 114 in contactwith layers 104 and 106 of the dummy gate and a second, superficial,layer 116, of silicon nitride covering the oxide layer. The purpose ofthe first spacer layer 114 is essentially to limit contact stresses withthe layers of material of the dummy gate, and especially with thepolycrystalline silicone. It also limits the contact stresses with asmall portion of substrate which it touches at the base of the dummygate.

The role of the second spacer layer is essentially to protect the dummygate from subsequent treatments in the method, in particular fromoxidation treatments.

The formation of the side spacers may be made using techniques known inthemselves which for the most part comprise the depositing of selectedmaterials over the entire wafer, followed by anisotropic etching ofthese materials so as only to leave a small thickness on the sides ofthe dummy gate.

Optionally, after the formation of the side spacers, a second implantingof impurities may be conducted at a higher dose. The second implantingthen uses the dummy gate, widened by the side spacers, as implantationmask. With this second implanting it is possible to obtain gradualsource and drain regions 118, 120 in the substrate, with doping whichdecreases towards channel 121 located under the dummy gate 112. Thegradual nature of the source and drain regions is not shown in thefigures for reasons of clarity.

FIG. 3 shows a following step which consists of performing selectivesiliciding of the substrate in the source and drain regions. Thisoperation comprises the depositing of a metal layer 124 such as, forexample, titanium or nickel, followed by heat treatment at sufficienttemperature to cause a siliciding reaction between the metal and siliconof the substrate.

Siliciding is qualified as selective insofar as it is limited to thezones in which the metal of layer 124 is directly in contact withsilicon. It can be seen in FIG. 3 that the metal layer 124 hasdisappeared above the source and drain regions to form superficiallayers of silicide 126, 128. On the other hand, the metal layer 124persists on the top and sides of the dummy gate 112. On these parts, thesilicon nitride of layers 106 and 116 of the dummy gate and spacers hasprevented siliciding.

FIG. 3, slightly enlarged relative to FIG. 2, shows the possibility ofpooling the source and drain with other components. In FIG. 3, thelocations of the gates of other components have been outlined in a chaindotted line.

FIG. 4 shows the formation of low resistivity accesses to the source anddrain regions. This operation comprises the conforming deposit of afirst, so-called contact, metal layer 130 followed by a second contactmetal layer 132. The first contact metal may be chosen from amongtungsten or titanium for example.

The second contact metal, preferably chosen to have greater resistanceto abrasion than the first contact metal, may for example be chosen fromamong tantalium, tantalium nitride, titanium nitride, . . . .

In the illustrated example, the overall thickness of the two layers ofcontact metal totals the height of the dummy gate or more, so that it issubsequently possible to perform polishing, stopping at the dummy gate.

The result of polishing is shown in FIG. 5. It can be seen thatpolishing is stopped precisely at the second layer 106 of material ofthe dummy gate, in this case the layer of silicon nitride.

The siliciding metal layer 124 comes to be removed from the top part ofthe dummy gate, and electric insulation of the source and drain regionscan be obtained. It is recalled that, outside the active region, whoselength is generally smaller than the length of the gate in a directionperpendicular to the plane of the figures, it is possible to useappropriate etching, in known manner, to fix the limits of the conductorparts and hence to avoid any short-circuiting between these parts. Inaddition, insulation is also obtained by means of an oxidation asdescribed below, with reference to FIG. 6 and conducted during asubsequent step of the method.

Through the use of two different contact materials, an upper surface 136with good planarity can be obtained.

FIG. 6 shows a subsequent step which consists of imparting an insulatingnature to the materials flush with the upper surface 136. During thisstep, oxidation is performed by subjecting the structure to an oxidizingatmosphere. Oxidation particularly concerns the contact metals alreadymentioned in the preceding description. To facilitate the reading ofFIG. 6, the oxidized parts are marked with the same references as thecorresponding non-oxidized parts but are followed by the letter a. Theoxidized parts 124 a, 130 a and 132 a are therefore respectively theoxidized superficial parts of the metal preserved on the sides of thegate, and initially used for siliciding the first contact metal and thesecond contact metal. Their oxidation imparts an electric insulatingnature to the metals.

FIG. 7 shows the structure obtained after removal of the dummy gate.Removal is made by selectively attacking the silicon nitride of thesecond layer 106 of the dummy gate, then by attacking thepolycrystalline silicon of the first layer. At the time of this etching,the oxide layer of pedestal 102 may be used as etching stop. This layeris then also removed. The etching agents used may for example be HBr orSF₆ for etching silicon nitride, and HBr+Cl₂ for etching thepolycrystalline silicon. The oxide may be removed with dilute HF. Duringthis step, part of the layers 124 a, 130 a and 132 a is also removed.Therefore, during the oxidation step in FIG. 6, the thickness of theoxide is sized so as to take into account this partial etching of layers124 a, 130 a and 132 a.

The removal of the dummy gate leaves behind a well denoted 140.

FIG. 8 shows the fabrication of the final gate. This operation comprisesthe formation of a gate insulating layer 148, for example by oxidizingthe silicon of the underlying substrate, or by depositing a dielectricmaterial, then depositing a layer of gate material 150, preferably in ametal chosen for example from among: W, TaN, W/TiN, Ti, TaN, Cu/TaN,W/Pt, N/Pt, W/Nb or W/RuCa.

Layer 150 may be a solid layer or optionally made up of a combination oftwo or more of the materials cited. The thickness of the layer or layersof gate 150 is sufficient to fill in the well left after removal of thedummy gate and to cover the upper plane surface 136 as defined bypolishing.

A second polishing operation, as shown in FIG. 9, makes it possible toremove the material of the gate layer 150 above the source and drain, soas only to maintain material in the well. The gate, which is flush withthe upper surface 136, is also denoted 150. The end component obtainedis a field-effect transistor and has a structure of damascene type.

The figures do not show the fabrication of contact pads on the gate,source and drain. These operations, well known in themselves in thefield of microelectronics are not, in the strict sense of the word, partof the method of fabricating the transistor.

FIGS. 10 and 11 show the fabrication of another component, a memory inparticular, using a structure such as described with reference to FIG.7.

A first gate layer 160 whose thickness is less than the depth of thewell 140 left by the dummy gate, that is to say less than the height ofthe removed dummy gate, is formed above gate insulating layer 148 whichlines the bottom of the well. The first gate layer 160 also covers theupper free surface 136 of the structure.

Above the first gate layer an inter-gate dielectric layer 162 isdeposited, whose thickness, added to the thickness of the first gatelayer, is also less than the height of the dummy gate (removed).

Finally, a second gate layer 164 is deposited on the inter-gate layer162. The thickness of the second gate layer is sufficient, together withthe other deposited layers, to fill in the well left after removal ofthe dummy gate.

It is to be specified that the above-mentioned layers may each be formedof a stack of several sub-layers. In particular, the inter-gate layer162 may be formed of a nitride/oxide/nitride stack chosen for having aparticularly high dielectric constant. The materials chosen for thefirst and second gate layers may be those mentioned previously for thefabrication of the transistor gate.

Polishing of the gate and inter-gate layers, stopping at the metaloxides 124 a, 130 a, 132 a, makes it possible to obtain a structure suchas shown in FIG. 11. It can be seen that the first gate layer, and theinter-gate layer, have a U shape section along a plane parallel to theplane of the figure substantially extending in a source-gate-draindirection. The second gate layer 154 fills in the U shape.

With this particular shape it is possible to increase the surfacesopposite one another between the first and second gate layers without,however, increasing the surfaces opposite one another between the firstgate layer and the substrate. Since the first and second gate layers,after polishing, respectively form the floating gate and the commandgate of a memory, the structure in FIG. 11 provides a high capacitybetween the command gate and the floating gate and a low capacitybetween the floating gate and the channel (substrate). Since the sourceand drain access resistances are also very low on account of the use ofthe contact metal, high frequency functioning for the memory can beachieved, both for reading and for writing.

When a transistor or a memory such as described above are integratedinto a circuit, contact points are made in the source, drain and gateregions. These comprise the formation of openings for example in theoxide layers which cover the source and drain, followed by thepositioning of an interconnection metal in the openings to connect thenon-oxidized contact metal to interconnection lines. Even though suchoperations no longer form part of the fabrication of the components andare well known in themselves, FIG. 12 illustrates an interconnectionoperation between the drain of a memory component such as previouslydescribed and a neighbouring component.

A layer of insulating material 170 such as SiO₂ is deposited on the freesurface 136 of the components, that is to say the surface obtained bythe last polishing. This layer prevents short-circuiting between aninterconnection material (not shown) and other component parts.

An opening 172 made in the insulating layer 170 extends through theoxidized parts 130 a, 132 a of the first and second layers of contactmetal to expose the non-oxidized parts 130, 132 of these layers. FIG. 12shows that the alignment requirements of opening 172 in the insulatinglayer 170 are not very high. The opening only needs to coincide with thechosen source or drain region, without necessarily corresponding to thecentre of this region. The fact that different materials are encounteredwhen making opening 172 accounts for the staircase bottom of the openingas shown in FIG. 12.

Cited Documents

-   [1] FR-A-2 757 312-   [2] FR-A-2 750 534

1. A method for fabricating an electronic component with a self-alignedsource, drain and gate, comprising the steps of: a) forming a dummy gateon a silicon substrate, said dummy gate defining a position for achannel of the component; b) at least one implantation of dopingimpurities in the substrate, to form a source and a drain on either sideof the channel, using the dummy gate as an implanting mask; c) forming ametal layer on the source, drain and dummy gate: d) superficial,self-aligned siliciding of the source and drain by selectivelysiliciding the metal layer on the source and drain; e) depositing atleast one contact metal layer having a total thickness greater than aheight of the dummy gate, polishing the at least one contact metal layerstopping at the dummy gate, and imparting an insulation characteristicto a surface region of the at least one contact metal layer and themetal layer on sides of the gate electrode; and f) replacing the dummygate by at least one final gate separated from the substrate by a gateinsulating layer, and electrically insulated from the source and drain.2. The method according to claim 1, wherein step e) comprises depositinga first metal layer and, above the first metal layer, a second metallayer having a greater mechanical resistance to polishing than the firstmetal layer, a thickness of the first metal layer being less than theheight of the dummy gate, and a total thickness of the first and secondmetal layers being greater than the height of the dummy gate.
 3. Themethod according to claim 2, wherein a metal of the first metal layer ischosen from among tungsten and titanium, and a metal of the second metallayer is chosen from among TaN, Ta and TiN.
 4. The method according toclaim 1, further comprising, before siliciding, forming side spacers onsides of the dummy gate.
 5. The method according to claim 4, wherein theside spacers are formed comprising an attachment layer in silicon oxide,in contact with the dummy gate, and a superficial layer in siliconnitride.
 6. The method according to claim 1, wherein the surfaceinsulation comprises superficially oxidizing the at least one contactmetal layer.
 7. The method according to claim 1, wherein the siliconsubstrate comprises a solid substrate.
 8. The method according to claim1, wherein the silicon substrate comprises a silicon on insulatorsubstrate.
 9. The method according to claim 1, wherein step f) comprisesremoving the dummy gate, forming the gate insulating layer, depositingat least one metal layer to form the final gate, having an overallthickness equal to or greater than the height of the removed dummy gate.10. The method according to claim 9, further comprising, after formingthe gate insulating layer, depositing a first gate metal layer,depositing at least one inter-gate dielectric layer, and depositing asecond gate metal layer.
 11. The method according to claim 1, whereinthe surface insulation comprises depositing a layer of dielectricmaterial.